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204
XMEGA A [MANUAL]
8077I–AVR–11/2012
The TWI bus is a simple and efficient method of interconnecting multiple devices on a serial bus. A device connected to
the bus can be a master or slave, where the master controls the bus and all communication.
Figure 19-1 on page 204 illustrates the TWI bus topology.
Figure 19-1. TWI bus topology.
A unique address is assigned to all slave devices connected to the bus, and the master will use this to address a slave
and initiate a data transaction.
Several masters can be connected to the same bus, called a multi-master environment. An arbitration mechanism is
provided for resolving bus ownership among masters, since only one master device may own the bus at any given time.
A device can contain both master and slave logic, and can emulate multiple slave devices by responding to more than
one address.
A master indicates the start of a transaction by issuing a START condition (S) on the bus. An address packet with a slave
address (ADDRESS) and an indication whether the master wishes to read or write data (R/W) are then sent. After all
data packets (DATA) are transferred, the master issues a STOP condition (P) on the bus to end the transaction. The
receiver must acknowledge (A) or not-acknowledge (A) each byte received.
Figure 19-2 on page 204 shows a TWI transaction.
Figure 19-2. Basic TWI transaction diagram topology for a 7-bit address bus .
The master provides the clock signal for the transaction, but a device connected to the bus is allowed to stretch the low-
level period of the clock to decrease the clock speed.
TWI
DEVICE #1
RP
RS
SDA
SCL
VCC
TWI
DEVICE #2
RS
TWI
DEVICE #N
RS
Note: RS is optional
P
S
ADDRESS
6 ... 0
R/W
ACK
7 ... 0
DATA
ACK/NACK
7 ... 0
DATA
SDA
SCL
S
A
A/A
R/W
ADDRESS
DATA
P
A
DATA
Address Packet
Data Packet #0
Transaction
Data Packet #1
Direction
The slave provides data on the bus
The master provides data on the bus
The master or slave can provide data on the bus
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